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| 32-bit arm ? cortex?-m3 microcontroller,up to 256kb flash and 32kb sram with 1 msps adc, usart, uart, spi, i 2 c, i 2 s, mctm, gptm, bftm, pdma, sci, crc, ebi and usb2.0 fs HT32F1656/ht32f1655 series datasheet revision: v1.00 date: ???? ??? ? 01 ? ???? ??? ? 01 ?
rev. 1.00 ? of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 table of contents table of contents 1 general description ........... ..................................................................................... 6 2 features ................................................................................................................... 7 core ....................................................................................................................................... 7 on-chip memor ? .................................................................................................................... 7 f ? ash memor ? contro ?? er ....................................................................................................... 7 reset contro ? unit ................................................................................................................. 8 c ? ock contro ? unit .................................................................................................................. 8 power management ............ ................................................................................................... 8 externa ? interr ? pt/event contro ?? er ........................................................................................ 9 ana ? og to digita ? converter .................................................................................................... 9 analog operational amplifer/comparator ........... .................................................................. 9 i/o ports ............ ................................................................................................................... 10 pwm generation and capt ? re timers C gptm .................................................................. 10 motor contro ? timer C mctm .............................................................................................. 10 basic f ? nction timer C bftm ............................................................................................. 11 watchdog timer ............ ....................................................................................................... 11 rea ? time c ? ock ................................................................................................................... 11 inter-integrated circ ? it C i ? c ................................................................................................ 1 ? seria ? periphera ? interface C spi ......................................................................................... 1 ? universa ? s ? nchrono ? s as ? nchrono ? s receiver transmitter C usart .............................. 1 ? universa ? as ? nchrono ? s receiver transmitter C uart ...................................................... 13 smart card interface C sci ................................................................................................. 13 inter-ic so ? nd C i ? s ............ ................................................................................................ 1 ? c ? c ? ic red ? ndanc ? check C crc ....................................................................................... 1 ? periphera ? direct memor ? access C pdma ......................................................................... 15 externa ? b ? s interface C ebi ............ .................................................................................... 15 universa ? seria ? b ? s device contro ?? er C usb .................................................................... 16 deb ? g s ? pport ..................................................................................................................... 16 package and operation temperat ? re .................................................................................. 16 3 overview ................................................................................................................ 17 device information ............................................................................................................... 17 b ? ock diagram ..................................................................................................................... 18 memor ? map ........................................................................................................................ 19 c ? ock str ? ct ? re ........... ......................................................................................................... ? 0 pin assignment .................................................................................................................... ? 1 rev. 1.00 3 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 table of contents table of contents 4 electrical characteristics ..................................................................................... 30 abso ?? te maxim ? m ratings ................................................................................................. 30 recommended dc operating conditions ........................................................................... 30 on-chip ldo vo ? tage reg ?? ator characteristics ................................................................. 30 power cons ? mption ............................................................................................................ 31 reset and s ? pp ?? monitor characteristics ........................................................................... 3 ? externa ? c ? ock characteristics ............................................................................................. 3 ? interna ? c ? ock characteristics .............................................................................................. 33 pll characteristics .............................................................................................................. 3 ? memor ? characteristics ....................................................................................................... 3 ? i/o port characteristics ........................................................................................................ 3 ? adc characteristics ........... ................................................................................................. 36 operation a ? amplifer/comparator characteristics ............ ................................................... 38 gptm/mctm characteristics .............................................................................................. 38 i ? c characteristics ............................................................................................................... 39 spi characteristics ........... ................................................................................................... ? 0 i ? s characteristics ............................................................................................................... ? 1 usb characteristics ............................................................................................................. ? 3 5 package information ............................................................................................ 44 ? 8-pin lqfp (7mm7mm) o ? t ? ine dimensions ................................................................... ? 5 6 ? -pin lqfp (7mm7mm) o ? t ? ine dimensions ................................................................... ? 6 100-pin lqfp (1 ? mm1 ? mm) o ? t ? ine dimensions ............ ................................................. ? 7 rev. 1.00 ? of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 list of tables list of tables tab ? e 1. ht3 ? f1656/1655 series feat ? res and periphera ? list ....... ....................................................... 17 tab ? e ? . ht3 ? f1656/55 series pin assignment for lqfp100 / 6 ? / ? 8 package ....... ............................. ?? tab ? e 3. ht3 ? f1656/55 pin description ...... ............................................................................................ ? 7 tab ? e ? . abso ?? te maxim ? m ratings ........................................................................................................ 30 tab ? e 5. recommended dc operating conditions .................................................................................. 30 tab ? e 6. ldo characteristics ...... ............................................................................................................. 30 tab ? e 7. power cons ? mption characteristics .......................................................................................... 31 tab ? e 8. lvd/bod characteristics ....... .................................................................................................... 3 ? tab ? e 9. high speed externa ? c ? ock (hse) characteristics ..................................................................... 3 ? tab ? e 10. low speed externa ? c ? ock (lse) characteristics .................................................................... 3 ? tab ? e 11. high speed interna ? c ? ock (hsi) characteristics ...................................................................... 33 tab ? e 1 ? . low speed interna ? c ? ock (lsi) characteristics ....................................................................... 33 tab ? e 13. pll characteristics .................................................................................................................. 33 tab ? e 1 ? . f ? ash memor ? characteristics .................................................................................................. 33 tab ? e 15. i/o port characteristics ............................................................................................................ 3 ? tab ? e 16. adc characteristics ................................................................................................................. 35 tab ? e 17. opa/cmp characteristics ........................................................................................................ 37 tab ? e 18. gptm/mctm characteristics .................................................................................................. 37 tab ? e 19. i ? c characteristics .................................................................................................................... 38 tab ? e ? 0. spi characteristics ................................................................................................................... 39 tab ? e ? 1. i ? s characteristics .................................................................................................................... ? 0 tab ? e ?? . usb dc e ? ectrica ? characteristics ........................................................................................... ?? tab ? e ? 3 usb ac e ? ectrica ? characteristics ............................................................................................. ?? rev. 1.00 5 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 list of tables list of figures list of figures fig ? re 1. ht3 ? f1656/1655 b ? ock diagram ............................................................................................. 18 fig ? re ? . ht3 ? f1656/1655 memor ? map ................................................................................................ 19 fig ? re 3. ht3 ? f1656/1655 c ? ock str ? ct ? re ............................................................................................ ? 0 fig ? re ? . ht3 ? f1656/1655 lqfp- ? 8 pin assignment ............................................................................ ? 1 fig ? re 5. ht3 ? f1656/1655 lqfp-6 ? pin assignment ............................................................................ ?? fig ? re 6. ht3 ? f1656/1655 lqfp-100 pin assignment .......................................................................... ? 3 fig ? re 7. adc samp ? ing network mode ? ................................................................................................. 36 fig ? re 8. i ? c timing diagrams ....... .......................................................................................................... 38 fig ? re 9. spi timing diagrams - spi master mode ................................................................................. 39 fig ? re 10. spi timing diagrams - spi s ? ave mode with cpha=1 ...... .................................................... ? 0 fig ? re 11. timing of i ? s master mode ....... ............................................................................................... ? 1 fig ? re 1 ? . timing of i ? s s ? ave mode ....................................................................................................... ? 1 fig ? re 13. usb signa ? rise time and fa ?? time and cross-point vo ? tage (v crs ) defnition ...... .............. ?? rev. 1.00 6 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 general description 1 general description the holtek HT32F1656/1655 devices are high performance, low power consumption 32-bit microcontrollers based around an arm ? cortex?-m3 processor core. the cortex?-m3 is a next-generation processor core which is tightly coupled with nested vectored interrupt controller (nvic), systick timer, and includes advanced debug support. the devices operate at a frequency of up to 72 mhz with a flash accelerator to obtain maximum effciency. they provide up to 256 kb of embedded flash memory for code/data storage and 32 kb of embedded sram memory for system operation and application program usage. a variety of peripherals, such as adc, i 2 c, usart, uart, spi, i 2 s, pdma, gptm, mctm, sci, ebi, crc- 16/32, usb2.0 fs, sw-dp (serial wire debug port), etc., are also implemented in the devices. several power saving modes provide the fexibility for maximum optimisation between wakeup latency and power consumption, an especially important consideration in low power applications. the above features ensure that the devices are suitable for use in a wide range of applications, especially in areas such as white goods application control, power monitors, alarm systems, consumer products, handheld equipment, data logging applications, motor control, fingerprint recognition and so on. rev. 1.00 7 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 general description features 2 features core ? 32-bit arm ? cortex?-m3 processor core ? up to 72 mhz operati ng frequency ? 1.25 dmips/mhz (dhrystone 2.1) ? single-cycle multiplication and hardware division ? integrated nested vectored interrupt controller (nvic) ? 24-bit systick timer the cortex?-m3 processor is a general-purpose 32-bit processor core especially suitable for products requiring high performance and low power consumption microcontrollers. it offers many special features such as a thumb-2 instruction set, hardware divider, low latency interrupt respond time, atomic bit-banding access and multiple buses for simultaneous accesses. the cortex?-m3 processor is based on the armv7 architecture and supports both thumb and thumb-2 instruction sets. on-chip memory ? up to 256 kb on-chip flash memory for instruction/data and option storage ? 32 kb on-chip sram ? supports multiple boot modes the arm ? cortex?-m3 processor is structured using harvard architecture which uses a separate bus structure to fetch instructions and load/store data. the instruction code and data are both located in the same memory address space but in different address ranges. the maximum address range of the cortex?-m3 is 4 gb due to its 32-bit bus address width. additionally, a pre-defned memory map is provided by the cortex?-m3 processor to reduce the software complexity of repeated implementation for different device vendors. however, some regions are used by the arm ? cortex?-m3 system peripherals. refer to the arm ? cortex?-m3 technical reference manual for more information. figure 2 shows the memory map of the HT32F1656/55 series of devices, including code, sram, peripheral, and other pre-defned regions. flash memory controller ? flash accelerator for maximum effciency ? 32-bit word programming with in system programming interface (isp) and in application programming (iap) ? flash protection capability to prevent illegal access the flash memory controller, fmc, provides all the necessary functions and pre-fetch buffer for the embedded on-chip flash memory. since the access speed of the flash memory is slower than the cpu, a wide access interface with a pre-fetch buffer and cache are provided for the flash memory in order to reduce the cpu waiting time which will cause cpu instruction execution delays. flash memory word program/page erase functions are also provided. rev. 1.00 8 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 features reset control unit ? supply supervisor: power-on reset - por brown-out detector - bod programmable low voltage detector - lvd the reset control unit , rstcu , has three kinds of reset, a power on reset, a system reset and an apb unit reset. the power on reset, known as a cold reset, resets the full system during power up. a system reset resets the processor core and peripheral ip components with the exception of the sw-dp controller. the resets can be triggered by an external signal, internal events and the reset generators. clock control unit ? external 4 to 16 mhz crystal oscillator ? external 32,768 hz crystal oscillator ? internal 8mhz rc oscillator trimmed to 2% accuracy at 3.3v operating voltage and 25c operating temperature ? internal 32 khz rc oscillator ? integrated system clock pll ? independent clock gating bits for peripheral clock sources the clock control unit, ckcu, provides a range of oscillator and clock functions. these include a high speed internal rc oscillator (hsi), a high speed external crystal oscillator (hse), a low speed internal rc oscillator (lsi), a low speed external crystal oscillator (lse), a phase lock loop (pll), a hse clock monitor, clock prescalers, clock multiplexers and clock gating circuitry. the clocks of the ahb, apb and cortex tm -m3 are derived from the system clock (ck_sys) which can come from the hsi, hse or pll. the watchdog timer and real time clock (rtc) use either the lsi or lse as their clock source. the maximum operating frequency of the system core clock (ck_ahb) can be up to 72 mhz. power management ? single 3.3 v power supply: 2.7 v to 3.6 v ? integrated 1.8 v ldo regulator for core and peripheral power supply ? v b at battery power supply for rtc and backup registers ? three power domains: 3.3 v, 1.8 v and backup ? four power saving modes: sleep, deep-sleep1, deep-sleep2, power-down power consumption can be regarded as one of the most important issues for many embedded system applications. accordingly the power control unit, pwrcu, in these devices provides many types of power saving modes such as sleep, deep-sleep1, deep-sleep2 and power-down mode. these operating modes reduce the power consumption and allow the application to achieve the best trade-off between the conficting demands of cpu operating time, speed and power consumption. rev. 1.00 9 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 features features external interrupt/event controller ? up to 16 exti lines with confgurable trigger source and type ? all gpio pins can be selected as exti trigger source ? source trigger type includes high level, low level, negative edge, positive edge, or both edge ? individual interrupt enable, wakeup enable and status bits for each exti line ? software interrupt trigger mode for each exti line ? integrated deglitch flter for short pulse blocking the external interrupt/event controller, exti, comprises 16 edge detectors which can generate a wake-up event or interrupt requests independently. each exti line can also be masked independently. analog to digital converter ? 12-bit sar adc engine ? up to 1 msps conversion rate - 1 s at 56 mhz, 1.17 s at 72 mhz ? up to 16 external analog input channels ? supply voltage range: 2.7 v ~ 3.6 v ? conversion range: v ref+ ~ v ref- a 12-bit multi-channel adc is integrated in the device. there are up to 16 multiplexed channels, which include external channels on which the external analog signals can be measured, and 2 internal channels. if the input voltage is required to remain within a specifc threshold window, an analog watchdog function will monitor and detect the se signal s . an interrupt will then be generated to inform the device that the input voltage is not within the pre set threshold level s. there are three conversion modes to convert an analog signal to digital data. the adc can be operated in one shot, continuous and discontinuous conversion modes. analog operational amplifer/comparator ? two operational amplifers or comparator function s which are software confgurable ? supply voltage range: 2.7 v ~ 3.6 v two operational amplifers/comparators (opa/cmp) are implemented within the devices. they can be confgured either as operational amplifers or as analog comparators. when confgured as comparators, they are capable of generating interrupts to the nvic. rev. 1.00 10 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 features i/o ports ? up to 80 gpios ? port a, b, c, d, e are mapped as 16 external interrupts - exti ? almost all i/o pins are 5 v-tolerant except for pins shared with analog inputs there are up to 80 general purpose i/o pins, gpio, named from pa0~pa15 to pe0~pe15 for the implementation of logic input/output functions. each of the gpio ports has a series of related control and confguration registers to maximi s e fexibility and to meet the requirements of a wide range of applications. the gpio ports are pin-shared with other alternative functions to obtain maximum functional flexibility on the package pins. the gpio pins can be used as alternative functional pins by confguring the corresponding registers regardless of the input or output pins. the external interrupts on the gpio pins of the device have related control and configuration registers in the external interrupt control unit , exti. pwm generation and capture timers C gptm ? two 16-bit general-purpose timers - gptm ? up to 4-channel with pwm, compare output or input capture function for each gptm ? external trigger input the general purpose timers, known as gptm0 and gptm1, consist of one 16-bit up/down- counter, four 16-bit capture/compare registers (ccrs), one 16-bit counter reload register (crr) and several control/status registers. they can be used for a variety of purposes including general time measurement, input signal pulse width measurement, output waveform generation such as single pulse generation, or pwm output generation. the gptm supports an encoder interface using a decoder with two inputs. motor control timer C mctm ? two 16-bit up, down, up/down auto-reload counters ? 16-bit programmable prescaler allowing division of the counter clock frequency by any factor between 1 and 65536 ? input capture function ? compare match output ? pwm waveform generation with edge aligned and centre-aligned counting mode s ? single pulse mode output ? complementary outputs with programmable dead-time insertion ? encoder interface controller with two inputs using quadrature decoder ? supports 3-phase motor control and hall sensor interface ? brake input to force the timers output signals in to a reset or fxed condition the motor control timer consists of a single 16-bit up/down counter; four 16-bit ccrs (capture/ compare register s ), single one 16-bit counter-reload register (crr), single 8-bit repetition counter and several control/status registers. it can be used for a variety of purposes including measuring the pulse width s of input signal s or generating output waveforms such as compare match output s , pwm output s or complementary pwm output s with dead-time insertion. the mctm supports an encoder interface controller to an incremental encoder with two inputs. th e mctm is capable of offering full functional support for motor control, hall sensor interfac ing and brake input. rev. 1.00 11 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 features features basic function timer C bftm ? two 32-bit compare/match count-up counters - no i/o control features ? one shot mode - counting stops after a match condition ? repetitive mode - restart counter after a match condition the basic function timer is a simple count-up 32-bit counter designed to measure time intervals and generate a one shot or repetitive interrupts. the bftm operates in two functional modes, repetitive or one shot mode. in the repetitive mode the bftm restarts the counter when a compare match event occurs. the bftm also supports a one shot mode which forces the counter to stop counting when a compare match event occurs. watchdog timer ? 12-bit down counter with 3-bit prescaler ? interrupt or reset event for the system ? programmable watchdog timer window function ? register write protection function the watchdog timer is a hardware timing circuit that can be used to detect system failures due to software malfunctions. it includes a 12-bit count- down counter, a prescaler, a wdt counter value register, a wdt delta value register, interrupt related circuits, wdt operation control circuitry and a wdt protection mechanism. the watchdog timer can be operated in an interrupt mode or a reset mode. the watchdog timer will generate an interrupt or a reset when the counter counts down and reaches a zero value. if the software does not reload the counter value before a watchdog timer underfow occurs, an interrupt or a reset will be generated when the counter underfows. in addition, an interrupt or reset is also generated if the software reloads the counter when the counter value is greater than or equal to the wdt delta value. this means the counter must be reloaded within a limited timing window using a specific method. the watchdog timer counter can be stopped while the processor is in the debug mode. there is a register write protect function which can be enabled to prevent it from changing the watchdog timer confguration unexpectedly. real time clock ? 32-bit up-counter with a programmable prescaler ? alarm function ? interrupt and wake-up event the real time clock, rtc for short , includes an apb interface, a 32-bit count- up counter, a control register, a prescaler, a compare register and a status register. most of the rtc circuits are located in the backup domain except for the apb interface. the apb interface is located in the v dd18 power domain. therefore, it is necessary to be isolated from the iso signal that comes from the power control unit when the v dd18 power domain is powered off, that is when the device enters the power-down mode. the rtc counter is used as a wakeup timer to generate a system resume signal from the power-down mode. rev. 1.00 1 ? of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 features inter-integrated circuit C i 2 c ? supports both master and slave modes with a frequency of up to 1 mhz ? provide an arbitration function and clock synchroni sation ? supports 7-bit and 10-bit addressing mode s and general call addressing ? supports slave multi-addressing mode with maskable address the i 2 c module is an internal circuit allowing communication with an external i 2 c interface which is an industry standard two line serial interface used for connection to external hardware. these two serial lines are known as a serial data line, sda, and a serial clock line, scl. the i 2 c module provides three data transfer rates: 1 . 100 khz in the standard mode, 2 . 400 khz in the fast mode and 3 . 1 mhz in the fast mode plus mode . the scl period generation register is used to setup different kinds of duty cycle implementation s for the scl pulse. the sda line which is connected directly to the i 2 c bus is a bi-directional data line between the master and slave devices and is used for data transmission and reception. the i 2 c module also has an arbitration detect function and clock synchronisation to prevent situation s where more than one master attempts to transmit data to the i 2 c bus at the same time. serial peripheral interface C spi ? supports both master and slave mode ? frequency of up to 36 mhz for master mode and 24mhz for slave mode ? fifo depth: 8 levels ? multi-master and multi-slave operation the serial peripheral interface, spi, provides an spi protocol data transmit and receive function in both master and slave mode. the spi interface uses 4 pins, which are the serial data input and output lines miso and mosi, the clock line, sck, and the slave select line, sel. one spi device acts as a master device which controls the data fow using the sel and sck signals to indicate the start of data communication and the data sampling rate. to receive a data byte, the streamed data bits are latched on a specifc clock edge and stored in the data register or in the rx fifo. data transmission is carried out in a similar way but in a reverse sequence. the mode fault detection provides a capability for multi-master applications. universal synchronous asynchronous receiver transmitter C usart ? supports both asynchronous and clocked synchronous serial communication modes ? asynchronous operating baud rate up to 4.5 mhz and synchronous operating rate up to 9 mhz ? full duplex communication ? fully programmable serial communication characteristics including: word length: 7, 8, or 9-bit character parity: even, odd, or no-parity bit generation and detection stop bit: 1 or 2 stop bit generation bit order: lsb-frst or msb-frst transfer ? error detection: parity, overrun, and frame error ? auto hardware fow control mode - rts, cts ? irda sir encoder and decoder ? rs485 mode with output enable control ? fifo depth: 16 x 9 bits for both receiver and transmitter rev. 1.00 13 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 features features the universal synchronous asynchronous receiver transceiver, usart, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. the usart is used to translate data between parallel and serial interfaces, and is commonly used for rs232 standard communication. the usart peripheral function supports four types of interrupt including line status interrupt, transmitter fifo empty interrupt, receiver threshold level reaching interrupt and time out interrupt. the usart module includes a 16-byte transmitter fifo, (tx_fifo) and a 16-byte receiver fifo (rx_fifo). the s oftware can detect a usart error status by reading the line status register, lsr. the status includes the type and the condition of transfer operations as well as several error conditions resulting from parity, overrun, framing and break events. universal asynchronous receiver transmitter C uart ? asynchronous serial communication operating baud-rate up to 4.5 mhz ? full duplex communication ? fully programmable serial communication characteristics including: word length: 7, 8, or 9-bit character parity: even, odd, or no-parity bit generation and detection stop bit: 1 or 2 stop bit generation bit order: lsb-frst or msb-frst transfer ? error detection: parity, overrun, and frame error ? fifo depth: 16 x 9 bits for both receiver and transmitter the universal asynchronous receiver transceiver, uart, provides a flexible full duplex data exchange using asynchronous transfer. the uart is used to translate data between parallel and serial interfaces, and is commonly used for rs232 standard communication. the uart peripheral function supports four types of interrupt including line status interrupt, transmitter fifo empty interrupt, receiver threshold level reaching interrupt and time out interrupt. the uart module includes a 16-byte transmitter fifo, (tx_fifo) and a 16-byte receiver fifo (rx_ fifo). the s oftware can detect a uart error status by reading the line status register, lsr. the status includes the type and the condition of transfer operations as well as several error conditions resulting from parity, overrun, framing and break events. smart card interface C sci ? supports iso 7816-3 standard ? character mode ? single transmit buffer and single receive buffer ? 11-bit etu (elementary time unit) counter ? 9-bit guard time counter ? 24-bit general purpose waiting time counter ? parity generation and checking ? automatic character retry on parity error detection in transmission and reception modes the smart card interface is compatible with the iso 7816-3 standard. this interface includes card insertion/removal detection, sci data transfer control logic and data buffers, internal timer counters and corresponding control logic circuits to perform all the necessary smart card operations. the smart card interface acts as a smart card reader to facilitate communication with the external smart card. the overall functions of the smart card interface are controlled by a series of registers including control and status registers together with several corresponding interrupts which are generated to get the attention of the microcontroller for sci transfer status. rev. 1.00 1 ? of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 features inter-ic sound C i 2 s ? master or slave mode ? mono and stereo ? i 2 s-justifed, left-justifed, and right-justifed mode ? 8/16/24/32-bit sample size with 32-bit channel extended ? 8 x 32-bit tx & rx fifo with pdma supported ? 8-bit fractional clock divider with rate control the i 2 s is a synchronous communication interface that can be used as a master or slave to exchange data with other audio peripherals, such as adcs or dacs. the i 2 s supports a variety of data formats. in addition to the stereo i 2 s -justifed, left-justifed and right-justifed mode s, there are mono pcm modes with 8/16/24/32-bit sample size. when the i 2 s operates in the master mode, then when using the fractional divider, it can provide an accurate sampling frequency output and support the rate control function and fne-tuning of the output frequency to avoid system problems caused by the cumulative frequency error between different devices. cyclic redundancy check C crc ? supports crc16 polynomial: 0x8005, x 16 +x 15 +x 2 +1 ? supports ccitt crc16 polynomial: 0x1021, x 16 +x 12 +x 5 +1 ? supports ieee-802.3 crc32 polynomial: 0x04c11db7, x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x+1 ? supports 1s complement, byte reverse & bit reverse operation on data and checksum ? supports byte, half-word & word data size ? programmable crc initial seed value ? crc computation executed in 1 ahb clock cycle for 8-bit data and 4 ahb clock cycles for 32- bit data ? supports pdma to complete a crc computation of a block of memory the crc calculation unit is an error detection technique test algorithm which is used to verify data transmission or storage data correctness. a crc calculation takes a data stream or a block of data as input and generates a 16- or 32-bit output remainder. ordinarily, a data stream is suffxed by a crc code and used as a checksum when being sent or stored. therefore, the received or restored data stream is calculated by the same generator polynomial as described above. if the new crc code result does not match the one calculated earlier, that means data stream contains a data error. rev. 1.00 15 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 features features peripheral direct memory access C pdma ? 8 channels with trigger source grouping ? 8-/16-/32-bit width data transfer ? supports address increment, decrement or fx ed mode ? 4-level programmable channel priority ? auto reload mode ? supports trigger source: adc, spi, usart, uart, i 2 c, i 2 s, ebi, gptm, mctm, sci and software request the peripheral d irect m emory a ccess controller , pdma , moves data between the peripherals and the system memory on the ahb bus. each pdma channel has a source address, destination address, block length and transfer count. the pdma can exclude the cpu intervention and avoid interrupt service routine execution. it improves system performance as the software does not need to join each data movement operation. external bus interface C ebi ? programmable interface for various memory types ? translate the ahb transactions into the appropriate external device protocol ? memory bank regions and independent chip select control for each memory bank ? programmable timings to support a wide range of devices ? includes page read mode ? automatic translation when the ahb transaction width and external memory interface width is different ? write buffer to decrease the stalling of the ahb write burst transaction ? supports multiplexed and non-multiplexed address and data line confgurations ? up to 25 address lines ? up to 16-bit data bus width the external bus interface is able to access external parallel interface devices such as sram, flash and lcd modules. t he interface is memory mapped into the internal address map of the cortex-m3. the data and address lines can be multiplexed in order to reduce the number of pins required to connect to the external devices. tthe read/write timing of the bus can be adjusted to meet the timing specifcation of the external devices. note the interface only supports asynchronous 8 or 16-bit bus interface. rev. 1.00 16 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 features universal serial bus device controller C usb ? complies with usb 2.0 full-speed (12mbps) specifcation ? on-chip usb full-speed transceiver ? 1 control endpoint (ep0) for control transfer ? 3 single-buffered endpoints for bulk and interrupt transfer ? 4 double-buffered endpoints for bulk, interrupt and isochronous transfer ? 1,024 bytes ep-sram used as the endpoint data buffers the usb device controller is compliant with the usb 2.0 full-speed specifcation. there is one control endpoint known as endpoint 0 and seven configurable endpoints. a 1024-byte sram is used as the endpoint buffer. each endpoint buffer size is programmable using corresponding registers, which provides maximum fexibility for various applications. the integrated usb full- speed transceiver helps to minimi s e the overall system complexity and cost. the usb functional block also contains the resume and suspend feature to meet the requirements of low-power consumption. debug support ? serial wire debug port - sw-dp ? 6 instruction comparators and 2 literal comparators for hardware breakpoint or code / literal patch es ? 4 comparators for hardware watchpoint s ? 1-bit asynchronous trace (traceswo) package and operation temperature ? 48/64/100-pin lqfp package ? operation temperature range: -40c to +85c rev. 1.00 17 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 features overview 3 overview device information table 1. HT32F1656/1655 series features and peripheral list peripherals HT32F1656 ht32f1655 main f ? ash (kb) ? 55 1 ? 8 option b ? tes f ? ash 1 1 sram (kb) 3 ? 3 ? timers mctm ? gptm ? bftm ? rtc 1 wdt 1 comm ? nication usb 1 spi ? usart ? uart ? i ? c ? i ? s 1 sci 1 ebi 1 crc-16/3 ? 1 exti 16 1 ? -bit adc n ? mber of channe ? s 1 16 channe ? s opa/comparator ? gpio up to 80 cpu freq ? enc ? up to 7 ? mhz operating vo ? tage ? .7v ~ 3.6v operating temperat ? re - ? 0 ~ +85 packages ? 8/6 ? /100-pin lqfp rev. 1.00 18 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 overview block diagram tpiu sw - dp apb1 apb0 ahb periphera?s f?ash memor? icode dcode cortex tm -m3 processor f max : 7? mhz s?stem nvic sram contro??er fmc contro? registers ckcu / rstcu contro? registers pdma contro? registers pdma 8 channe?s dma req?est interr?pt req?est usart 0 uart 0 afio exti spi 1 mosi ? miso sck ? sel powered b? v dd33 v ss33 v dd 33 pll f max : 1?? mhz por 1. 8 v ch 3 ~ ch0 eti boot 0 boot 1 c?ock and reset contro? bod lvd xtalin xtalout v ldoout v dd 18 hsi 8 mhz hse ? ~ 16 mhz power contro? b?s matrix af af af af af af af af ldo 1. 8 v powered b? v dd 18 usb contro? / data registers swclk swdio sda scl af usart 1 power s?pp?? : b?s : contro? signa? : a?ternate f?nction : af powered b? v dd 18 mosi ? miso sck ? sel af f?ash memor? interface tx ? rx rts / txe cts / sck tx ? rx rts / txe cts / sck ch 0 ~ ch ? ch 0 n ~ ch ?n ch 3 ? eti ? brk af xtal 3? kin xtal 3? kout af porb v bak 3. 3 v lsi 3? khz lse 3? ? 768 hz breg back?p domain v dd 33 v bat v ss33 v bak pwrsw rtc pwrcu nrst rtcout wakeup af af gptm 0 ~ 1 ana?og opa / cmp powered b? v dda v dda v ssa cn 0 ? cp 0 aout 0 cn 1 ? cp 1 aout 1 opa / cmp adc _ in 0 ... adc _ in 15 af af i? c 0 ~ 1 adc 1? - bit sar adc traceswo mctm 0 bftm 0 ~ 1 sci af mpu clk ? dio? det ahb to apb bridge externa? b?s interafce usb device af dp dm wdt af ad 0~ ad 15 a0~a ?? cs 0~ cs 3 oe? wr ale ? rdy bl 0~ bl 1 sram gpio a~e pa ~ pe [ 15 :0] spi 0 af tx ? rx af uart 1 tx ? rx i?s mclk ? bclk ws ? sdo ? sdi crc - 16 / 3? ch 0 ~ ch ? ch 0 n ~ ch ?n ch 3 ? eti ? brk af mctm 1 figure 1. HT32F1656/1655 block diagram rev. 1.00 19 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 overview overview memory map usb sram 0x?00a_a000 reserved reserved 0x?009_a000 reserved reserved reserved reserved reserved reserved 0x?00?_7000 reserved reserved reserved usb gpioa?b?c?d?e ebi up to ?56 kb on-chip f?ash 0x0000_0000 reserved 0x000?_0000 boot ?oader 0x1f00_0000 reserved 0x1f00_?000 option b?te a?ias 0x1ff0_0000 up to ?56 kb 8 kb 1 kb reserved 0x1ff0_0?00 code sram periphera? 3? kb on-chip sram 0x?000_0000 reserved 0x?000_8000 sram bit band a?ias 0x??00_0000 reserved 0x???0_0000 3? kb ? mb apb periphera?s 0x?000_0000 ahb periphera?s 0x?008_0000 reserved 0x?010_0000 apb/ahb bit band a?ias 0x??00_0000 reserved 0x??00_0000 private periphera? b?s 0xe000_0000 reserved 0xe010_0000 0xffff_ffff 51? kb 51? kb 3? mb usart0 0x?000_0000 uart0 0x?000_1000 spi0 0x?000_?000 reserved 0x?000_5000 adc 0x?001_0000 0x?001_1000 reserved opa/cmp 0x?001_8000 0x?001_9000 afio 0x?00?_?000 reserved 0x?00?_3000 exti 0x?00?_?000 i?s 0x?00?_6000 mctm0 0x?00?_c000 0x?00?_d000 mctm1 usart1 0x?00?_0000 uart1 0x?00?_1000 sci 0x?00?_3000 reserved 0x?00?_5000 spi1 0x?00?_?000 i?c0 0x?00?_8000 0x?00?_a000 i?c1 0x?00?_9000 reserved 0x?006_9000 wdt 0x?006_8000 reserved 0x?006_b000 rtc/pwrcu 0x?006_a000 gptm0 0x?006_e000 reserved 0x?007_0000 gptm1 0x?006_f000 bftm0 0x?007_6000 reserved 0x?007_8000 bftm1 0x?007_7000 apb0 apb1 fmc 0x?008_0000 reserved 0x?008_?000 ckcu/rstcu 0x?008_8000 crc 0x?008_a000 pdma 0x?009_0000 0x?009_8000 0x?00a_8000 reserved 0x?00b_0000 0x?00f_ffff ahb ebi se?ection bank reserved 0x6000_0000 0x7000_0000 6? mb x ? 0x?000_?000 0x?00?_5000 0x?00?_e000 0x?00?_?000 0x?008_c000 0x?009_?000 0x?00a_c000 0x?00b_a000 figure 2. HT32F1656/1655 memory map rev. 1.00 ? 0 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 overview clock structure ?-16 mhz hse xtal 8 mhz hsi rc 3? khz lsi rc legend: hse = high speed externa? c?ock hsi = high speed interna? c?ock lse = low speed externa? c?ock lsi = low speed interna? c?ock 3?.768 khz lse osc wdtsrc pllsrc ahb presca?er 1?????8 fclk ( free r?nning c?ock) hclkd ( to pdma) stclk (to s?stick) adc presca?er ????6?8?16... ck_adc f ck_ahb,max = 72mhz ck_wdt wdten ck_ref ck_hsi/16 ck_hse/16 ck_sys/16 ckout ckoutsrc[?:0] hseen hsien lseen (note1) lsien (note1) f ck_sys,max = 144mhz ck_lsi ck_lse ck_ahb/16 ck_hsi ck_hse pclk ( opax? afio? adc? spix? usartx? uartx? i?cx? i?s? gptmx? mctmx? bftmx? exti? rtc? sci? wdt) pll c?ock monitor pllen ck_usart0 ck_usart1 ck_uart0 ck_uart1 f ck_usartn,max = 72mhz ck_lse ck_pll urnen pdmaen opa0en wdtren adcen presca?er 1?? f ck_pll,max = 144mhz ck_lsi hclks ( to sram) hclkf ( to f?ash) cm3en fmcen cm3en sramen 1 0 rtcsrc (note1) ck_rtc rtcen (note1) 1 0 1 0 note 1: those contro? bits are ?ocated at rtc contro? register (rtc_ctrl) ck_ahb 000 001 010 011 100 101 110 ck_sys sw[1:0] 0x 11 10 8 ck_usb f ck_usb,max = 48mhz usben presca?er 1???3 hclkc ( to cortex tm -m3) cm3en (contro? b? hw) presca?er 1~3? ck_ref ck_ebi ( to ebi) ebien divider 2 ckrefpre hclkbm ( to b?s matrix) cm3en bmen hclkapb0 ( to apb0 bridge) cm3en apb0en hclkapb1 ( to apb1 bridge) cm3en apb1en ck_crc ( to crc) crcen ck_gpio ( to gpio port) gpioeen gpioaen ckrefen figure 3. HT32F1656/1655 clock structure rev. 1.00 ? 1 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 overview overview pin assignment ?8 ?7 ?6 ?5 ?? ?3 ?? ?1 ?0 39 38 1 ? 3 ? 5 6 7 8 9 10 11 13 1? 15 16 17 18 19 ?0 ?1 ?? ?3 35 3? 33 3? 31 30 ?9 ?8 ?7 ?6 ?5 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 vdd 33_1 usbdm / pb 12 usbdp / pb 13 vss 33_3 vdd 33_3 pb 1 pb 0 pa 15 pa 14 pa 10 pa 9_ boot 1 pa 8_ boot 0 xtalin af 0 ( default ) af 0 (default) af 0 (default) vldoin vssldo nrst v b at xtal32 k in xtal32 k out rtcout vss33 _2 xtalout vdd33 _2 vssa p b 9 vdda p b 11 p b 10 p b 8 p b 7 p b 6 p b 5 p b 4 p b 2 p33 p33 bak 5vt bak p33 bak 33 v bak 33 v bak 5vt 5vt 5vt 5vt p18 usb usb 33v 33v 33v 33v 33v 33v 33v 33 v 33 v 33 v 33 v ap ap p33 ap p18 33 v 5vt 5vt 3.3 v digital power pad 3.3 v analog power pad 1.8 v power pad 3.3 v i / o pad 5 v t olerance i/ o pad high current output 5 v t olerance i/ o pad holtek ht 32f1656/1655 lqfp -48 37 1? ?? 36 vldoout p b 3 af 0 ( default ) 33v vss 33_1 p33 p33 33v 33v p33 p33 5vt 33 v 33 v p33 p33 5vt 5vt 5vt 5vt 5vt 5vt 5vt 5vt 5vt 5vt usb usb phy pad swclk traceswo swdio bak backup domain pad pa 11 pa 12 pa 13 pc13 pc14 pc15 p b 14 p b 15 af 1 af1 figure 4. HT32F1656/1655 lqfp-48 pin assignment rev. 1.00 ?? of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 overview 6? 63 6? 61 60 59 58 57 56 55 5? 1 ? 3 ? 5 6 7 8 9 10 15 17 18 19 ?0 ?1 ?? ?3 ?? ?5 ?6 ?7 ?7 ?6 ?5 ?? ?3 ?? ?1 ?0 39 38 37 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 vdd 33_1 usbdm / pb 12 usbdp / pb 13 vss 33_3 vdd33_3 pb 1 pb 0 pa 15 pa 14 pa 10 xtalin af 0 ( default ) af 1 af 0 (default) af 0 (default) af1 vldoin vssldo nrst v b at xtal32 k in xtal32 k out pc13 pc14 rtcout pc15 p b 14 p b 15 vss33 _2 xtalout vdd33 _2 vssa p b 9 vdda p b 11 p b 10 p b 8 p b 7 p b 6 pc7 p33 p33 bak 5vt bak p33 bak 33 v bak 33 v bak 5vt 5vt 5vt 5vt p18 usb usb 33v 33v 33v 33v 33v 33v 33v 33 v 33 v 33 v 33 v ap ap p33 ap p18 33 v 5vt 5vt 3.3 v digital power pad 3.3 v analog power pad 1.8 v power pad 3.3 v i / o pad 5 v t olerance i/ o pad high current output 5 v t olerance i/ o pad holtek ht 32f1656/1655 lqfp -64 53 16 ?8 ?8 vldoout pc8 af 0 ( default ) 33v vss 33_1 p33 p33 33v pa 13 pa 12 pa 11 p33 p33 5vt 5vt 33 v 33 v 5vt 5vt p33 p33 11 1? 13 pc 9 pc 11 pc 12 1? pc 10 ?9 30 31 pc 0 pd 0 pc1 pc2 3? 33v 5? 51 50 p b 5 p b 4 p b 2 ?9 p b 3 36 35 3? 33 pa 9_ boot 1 pa 8_ boot 0 pc 3 5vt 5vt 33v 33v 33v 33v 5vt pc 5 pc 4 pc 6 p33 p33 vdd33 _ 4 vss33 _4 5vt 5vt 5vt 5vt 5vt 5vt 5vt 5vt 5vt 5vt 5vt 5vt 5vt usb usb phy pad 5vt swclk traceswo swdio bak backup domain pad figure 5. HT32F1656/1655 lqfp-64 pin assignment rev. 1.00 ? 3 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 overview overview 100 99 98 97 96 95 9? 93 9? 91 81 1 ? 3 ? 5 6 7 8 1? 15 ?? ?6 ?7 ?8 ?9 30 31 3? 33 3? 35 36 66 65 6? 63 6? 61 60 59 58 57 56 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 vdd 33_1 usbdm usbdp vss 33 _3 vdd 33_3 pb 1 pb 0 pa 15 pa 14 swclk traceswo pa 10 xtalin af 0 ( default ) af 1 af 0 (default) af 0 (default) af1 vldoin vssldo nrst v b at xtal32 k in xtal32 k out pc13 pc14 rtcout pc15 p b 14 p b 15 vss33 _2 xtalout vdd33 _2 vssa p b 9 vdda p b 11 p b 10 p b 8 p b 7 p b 6 pc7 p33 p33 bak 5vt bak p33 bak 33 v bak 33 v bak 5vt 5vt 5vt 5vt p18 usb usb 33v 33v 33v 33v 33v 33v 33v 33 v 33 v 33 v 33 v ap ap p33 ap p18 33 v 5vt 5vt 3.3 v digital power pad 3.3 v analog power pad 1.8 v power pad 3.3 v i / o pad 5 v t olerance i/ o pad high current output 5 v t olerance i/ o pad holtek ht 32f1656/1655 lqfp -100 80 ?3 37 67 vldoout swdio pc8 af 0 ( default ) 33v vss 33_1 p33 p33 33 v pa 13 pa 12 pa 11 p33 p33 5vt 5vt 5vt 5vt p33 p33 9 10 11 pe 8 pe 10 pe 11 1? pe 9 38 39 ?0 pd1 pd 0 pd2 pd3 ?1 33 v 79 78 77 p b 5 p b 4 p b 2 76 p b 3 55 5? 53 5? pa 9_ boot 1 pa 8_ boot 0 pd 8 5vt 5vt 33v 33v 33v 33v 5vt pc 5 pc 4 pc 6 5vt 5vt 5vt 5vt 5vt 5vt 5vt 5vt 5vt usb usb phy pad pe 12 13 33v 16 17 18 pc 9 pc 11 pc 12 19 pc 10 33v 33v 33v 33v pd 6 ?0 33v ?1 pb 12 pb 13 ?? 33v 33 v nc ?5 ?? ?3 pd4 pd5 pc 0 ?? ?5 ?6 pc1 pc2 pc3 ?7 5vt 5vt 5vt ?8 ?9 50 5vt 83 pe1 8? pe2 5vt 5vt 85 pe3 8? 5vt 87 86 pe4 5vt 89 pe5 88 pe6 5vt 5vt 90 pe7 5vt 51 pd 7 68 pd 9 69 pd 10 70 pd 11 7? 71 pd 13 pd 12 5vt 5vt 7? 73 pd 15 pd 14 5vt 5vt 75 pe 0 5vt pe13 pe14 pe15 5vt 5vt 5vt p33 p33 vdd33 _4 vss33 _4 33v 33v ap ap vref- vref+ 5vt 5vt 5vt 5vt 5vt 5vt 5vt 5vt 5vt 5vt 5vt bak backup domain pad figure 6. HT32F1656/1655 lqfp-100 pin assignment rev. 1.00 ?? of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 overview tab ? e ? . ht3 ? f1656/55 series pin assignment for lqfp100 / 6 ? / ? 8 package package alternate function number af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 lqfp -100 lqfp -64 lqfp -48 system default gpio adc cmp mctm /gptm spi usart /uart i 2 c smc ebi i 2 s n/a n/a n/a n/a system other 1 1 1 pa0 adc_in0 gt1_ch0 usr0_rts i ? c1_scl sci_clk i ? s_ws ? ? ? pa1 adc_in1 gt1_ch1 usr0_cts i ? c1_sda sci_dio i ? s_ bclk 3 3 3 pa ? adc_in ? gt1_ch ? usr0_tx i ? s_ sdo ? ? ? pa3 adc_in3 gt1_ch3 usr0_rx i ? s_sdi 5 5 5 pa ? adc_in ? gt0_ch0 spi0_sck usr1_tx i ? c0_scl 6 6 6 pa5 adc_in5 gt0_ch1 spi0_mosi usr1_rx i ? c0_sda 7 7 7 pa6 adc_in6 gt0_ch ? spi0_miso usr1_rts 8 8 8 pa7 adc_in7 gt0_ch3 spi0_sel usr1_cts i ? s_ mclk 9 pe8 adc_in8 spi1_sel usr0_rts 10 pe9 adc_in9 spi1_sck usr0_cts 11 pe10 adc_in10 spi1_mosi usr0_tx 1 ? pe11 adc_in11 spi1_miso usr0_rx 13 pe1 ? adc_in1 ? 1 ? 9 9 vdd33_1 15 10 10 vss33_1 16 11 pc9 adc_in13 gt0_ch0 spi1_sel ur0_tx i ? c1_scl 17 1 ? pc10 adc_in1 ? gt0_ch1 spi1_sck ur0_rx i ? c1_sda 18 13 pc11 adc_in15 gt0_ch ? spi1_mosi 19 1 ? pc1 ? gt0_ch3 spi1_miso ? 0 pd6 gt0_eti ebi_ ardy ? 1 15 11 pb1 ? mt1_ch ? i ? c0_scl ?? 15 11 usbdm ? 3 16 1 ? usbdp ?? 16 1 ? pb13 mt1_ ch ? n i ? c0_sda ? 5 n.c. ? 6 17 13 vldoout ? 7 18 1 ? vldoin ? 8 19 15 vssldo ? 9 ? 0 16 nrst 30 ? 1 17 vbat 31 ?? 18 xtal3 ? kin pc13 3 ? ? 3 19 xtal3 ? kout pc1 ? 33 ?? ? 0 rtcout pc15_ wakeup 3 ? ? 5 pd0 mt1_eti i ? c0_sda ebi_ a18 i ? s_sdi 35 pe13 i ? c0_scl ebi_ a19 i ? s_ mclk 36 pe1 ? gt1_eti ebi_ a ? 0 i ? s_ws 37 pe15 gt1_ch0 ur0_tx ebi_ a ? 1 38 ? 6 ? 1 xtalin pb1 ? 39 ? 7 ?? xtalout pb15 ? 0 ? 8 ? 3 vdd33_ ? rev. 1.00 ? 5 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 overview overview package alternate function number af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 lqfp -100 lqfp -64 lqfp -48 system default gpio adc cmp mctm /gptm spi usart /uart i 2 c smc ebi i 2 s n/a n/a n/a n/a system other ? 1 ? 9 ?? vss33_ ? ?? pd1 gt1_ch1 ur0_rx ebi_ a ?? i ? s_ bclk ? 3 pd ? gt1_ch ? ebi_ a ? 3 i ? s_ sdo ?? pd3 gt1_ch3 ebi_ a ?? i ? s_sdi ? 5 pd ? mt1_ch0 spi0_sel i ? c1_scl ebi_ a16 i ? s_ mclk ? 6 pd5 mt1_ ch0n spi0_sck i ? c1_sda ebi_ a17 ? 7 30 pc0 gt1_ch0 spi1_sel ebi_ ad13 i ? s_ws ? 8 31 pc1 gt1_ch1 spi1_sck ebi_ ad1 ? i ? s_ bclk ? 9 3 ? pc ? gt1_ch ? spi1_mosi ur1_tx i ? c0_scl ebi_ ad15 i ? s_ sdo 50 33 pc3 gt1_ch3 spi1_miso ur1_rx i ? c0_sda ebi_ cs3 i ? s_sdi 51 pd7 i ? c1_scl sci_clk ebi_ a ? 5 ? pd8 i ? c1_sda sci_dio ebi_ a0 53 3 ? ? 5 pa8_boot0 usr0_tx i ? s_ mclk ckout 5 ? 35 ? 6 pa9_boot1 spi0_mosi ebi_ a1 i ? s_ws 55 36 ? 7 pa10 mt1_ch1 usr0_rx sci_det 56 37 ? 8 traceswo pa11 mt1_ ch1n spi0_miso ebi_ a0 i ? s_ mclk traceswo 57 38 ? 9 swclk pa1 ? 58 39 30 swdio pa13 59 ? 0 31 pa1 ? mt0_ch0 spi1_sel usr1_tx sci_clk ebi_ ad0 60 ? 1 3 ? pa15 mt0_ ch0n spi1_sck usr1_rx sci_dio ebi_ ad1 61 ?? vdd33_3 6 ? ? 3 vss33_3 63 ?? 33 pb0 mt0_ch1 spi1_mosi usr0_tx i ? c0_scl ebi_ ad ? 6 ? ? 5 3 ? pb1 mt0_ ch1n spi1_miso usr0_rx i ? c0_sda ebi_ ad3 65 ? 6 pc ? mt1_ch ? usr1_rts sci_clk ebi_ ad10 66 ? 7 pc5 mt1_ ch ? n usr1_cts sci_dio ebi_ ad11 67 ? 8 pc6 mt1_ch3 sci_det ebi_ ad1 ? 68 pd9 spi0_sel ebi_ a3 69 pd10 spi0_sck ebi_ a ? 70 pd11 spi0_mosi ebi_ a5 71 pd1 ? spi0_miso ebi_ a6 7 ? pd13 spi1_sel ebi_ a7 73 pd1 ? spi1_sck ebi_ a8 7 ? pd15 spi1_mosi ebi_ a9 75 pe0 spi1_miso ebi_ a10 35 vdd33_3 36 vss33_3 76 ? 9 37 pb ? mt0_ch ? spi0_sel ur0_tx ebi_ ad ? 77 50 38 pb3 mt0_ ch ? n spi0_sck ur0_rx ebi_ ad5 78 51 39 pb ? mt0_brk spi0_mosi ur1_tx ebi_ ad6 79 5 ? ? 0 pb5 mt1_brk spi0_miso ur1_rx ebi_ ad7 rev. 1.00 ? 6 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 overview package alternate function number af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 lqfp -100 lqfp -64 lqfp -48 system default gpio adc cmp mctm /gptm spi usart /uart i 2 c smc ebi i 2 s n/a n/a n/a n/a system other 80 53 pc7 mt0_ch3 i ? c0_scl ebi_ ad8 81 5 ? pc8 mt0_eti i ? c0_sda ebi_ ad9 8 ? pe1 mt1_ch0 usr1_tx sci_clk ebi_ a11 83 pe ? mt1_ ch0n sci_dio ebi_ a1 ? 8 ? pe3 mt1_ch1 ebi_ a13 85 55 vdd33_ ? 86 56 vss33_ ? 87 pe ? mt1_ ch1n i ? c1_scl ebi_ a1 ? 88 pe5 mt1_ch ? usr1_rx i ? c1_sda ebi_ a15 89 pe6 mt1_ ch ? n usr1_rts ebi_ bl0 i ? s_ bclk 90 pe7 mt1_brk usr1_cts ebi_ bl1 i ? s_ mclk 91 57 ? 1 pb6 cn0 mt1_ch0 spi1_sel ur1_tx ebi_ oe i ? s_ mclk 9 ? 58 ?? pb7 cp0 mt1_ ch0n spi1_sck ebi_ cs0 93 59 ? 3 pb8 cout0 spi1_mosi ur1_rx ebi_ we 9 ? 60 ?? pb9 cn1 mt1_ch ? spi1_miso ur0_tx ebi_ ale i ? s_ bclk 95 61 ? 5 pb10 cp1 mt1_ ch ? n i ? c1_scl ebi_ cs1 i ? s_ sdo 96 6 ? ? 6 pb11 cout1 mt1_ch3 ur0_rx i ? c1_sda ebi_ cs ? i ? s_sdi 97 63 ? 7 vdda 98 63 ? 7 vref+ 99 6 ? ? 8 vref- 100 6 ? ? 8 vssa rev. 1.00 ? 7 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 overview overview table 3. HT32F1656/55 pin description pin number pin name type (note1) io structure (note2) output driving description lqfp 100 lqfp 64 lqfp 48 default function (af0) 1 1 1 pa0 ai/o 33v ? /8ma pa0 ? ? ? pa1 ai/o 33v ? /8ma pa1 3 3 3 pa ? ai/o 33v ? /8ma pa ? ? ? ? pa3 ai/o 33v ? /8ma pa3 5 5 5 pa ? ai/o 33v ? /8ma pa ? 6 6 6 pa5 ai/o 33v ? /8ma pa5 7 7 7 pa6 ai/o 33v ? /8ma pa6 8 8 8 pa7 ai/o 33v ? /8ma pa7 9 pe8 ai/o 33v ? /8ma pe8 10 pe9 ai/o 33v ? /8ma pe9 11 pe10 ai/o 33v ? /8ma pe10 1 ? pe11 ai/o 33v ? /8ma pe11 13 pe1 ? ai/o 33v ? /8ma pe1 ? 1 ? 9 9 vdd33_1 p 3.3 v vo ? tage for digita ? i/o 15 10 10 vss33_1 p gro ? nd reference for digita ? i/o 16 11 pc9 ai/o 33v ? /8ma pc9 17 1 ? pc10 ai/o 33v ? /8ma pc10 18 13 pc11 ai/o 33v ? /8ma pc11 19 1 ? pc1 ? i/o 33v ? /8ma pc1 ? ? 0 pd6 i/o 33v ? /8ma pd6 ? 1 15 11 pb1 ? i/o 5vt 8ma pb1 ? ?? 15 11 usbdm ai/o usb differentia ? data b ? s conforming to the universa ? seria ? b ? s standard. ? 3 16 1 ? usbdp ai/o usb differentia ? data b ? s conforming to the universa ? seria ? b ? s standard. ?? 16 1 ? pb13 i/o 5vt 8ma pb13 ? 5 nc no connection ? 6 17 13 vldoout p ldo power 1.8 v o ? tp ? t it is recommended to connect a capacitor ? denoted as cldo ? as c ? ose as possib ? e between this pin and vssldo. ? 7 18 1 ? vldoin p ldo power 3.3 v inp ? t connected to the power switch circ ? itr ? for the interna ? back ? p domain. ? 8 19 15 vssldo p ldo gro ? nd reference ? 9 ? 0 16 nrst i(bk) 5vt_pu externa ? reset pin and externa ? wake ? p pin in the power-down mode 30 ? 1 17 vbat p batter ? power inp ? t for the back ? p domain 31 ?? 18 pc13 ai/o (bk) 33v 1ma xtal3 ? kin 3 ? ? 3 19 pc1 ? ai/o (bk) 33v 1ma xtal3 ? kout 33 ?? ? 0 pc15 i/o (bk) 5vt 1ma rtcout 3 ? ? 5 pd0 i/o 5vt 8ma pd0 rev. 1.00 ? 8 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 overview pin number pin name type (note1) io structure (note2) output driving description lqfp 100 lqfp 64 lqfp 48 default function (af0) 35 pe13 i/o 5vt 8ma pe13 36 pe1 ? i/o 5vt 8ma pe1 ? 37 pe15 i/o 5vt 8ma pe15 38 ? 6 ? 1 pb1 ? ai/o 33v ? /8ma xtalin 39 ? 7 ?? pb15 ai/o 33v ? /8ma xtalout ? 0 ? 8 ? 3 vdd33_ ? p 3.3 v vo ? tage for digita ? i/o ? 1 ? 9 ?? vss33_ ? p gro ? nd reference for digita ? i/o ?? pd1 i/o 5vt 8ma pd1 ? 3 pd ? i/o 5vt 8ma pd ? ?? pd3 i/o 5vt 8ma pd3 ? 5 pd ? i/o 5vt 8ma pd ? ? 6 pd5 i/o 5vt 8ma pd5 ? 7 30 pc0 i/o 5vt 1 ? ma pc0 ? 8 31 pc1 i/o 5vt 1 ? ma pc1 ? 9 3 ? pc ? i/o 5vt 1 ? ma pc ? 50 33 pc3 i/o 5vt 1 ? ma pc3 51 pd7 i/o 5vt 8ma pd7 5 ? pd8 i/o 5vt 8ma pd8 53 3 ? ? 5 pa8 i/o 5vt_pu 1 ? ma pa8 5 ? 35 ? 6 pa9 i/o 5vt_pu 1 ? ma pa9 55 36 ? 7 pa10 i/o 5vt 8ma pa10 56 37 ? 8 pa11 i/o 5vt 8ma traceswo 57 38 ? 9 pa1 ? i/o 5vt_pu 8ma swclk 58 39 30 pa13 i/o 5vt_pu 8ma swdio 59 ? 0 31 pa1 ? i/o 5vt_pu 1 ? ma pa1 ? 60 ? 1 3 ? pa15 i/o 5vt_pu 1 ? ma pa15 61 ?? vdd33_3 p 3.3 v vo ? tage for digita ? i/o 6 ? ? 3 vss33_3 p gro ? nd reference for digita ? i/o 63 ?? 33 pb0 i/o 5vt 1 ? ma pb0 6 ? ? 5 3 ? pb1 i/o 5vt 1 ? ma pb1 65 ? 6 pc ? i/o 5vt 8ma pc ? 66 ? 7 pc5 i/o 5vt 8ma pc5 67 ? 8 pc6 i/o 5vt 8ma pc6 68 pd9 i/o 5vt 8ma pd9 69 pd10 i/o 5vt 8ma pd10 70 pd11 i/o 5vt 8ma pd11 71 pd1 ? i/o 5vt 8ma pd1 ? 7 ? pd13 i/o 5vt 8ma pd13 73 pd1 ? i/o 5vt 8ma pd1 ? 7 ? pd15 i/o 5vt 8ma pd15 75 pe0 i/o 5vt 8ma pe0 rev. 1.00 ? 9 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 overview overview pin number pin name type (note1) io structure (note2) output driving description lqfp 100 lqfp 64 lqfp 48 default function (af0) 35 vdd33_3 p 3.3 v vo ? tage for digita ? i/o 36 vss33_3 p gro ? nd reference for digita ? i/o 76 ? 9 37 pb ? i/o 5vt 1 ? ma pb ? 77 50 38 pb3 i/o 5vt 1 ? ma pb3 78 51 39 pb ? i/o 5vt 1 ? ma pb ? 79 5 ? ? 0 pb5 i/o 5vt 1 ? ma pb5 80 53 pc7 i/o 5vt 8ma pc7 81 5 ? pc8 i/o 5vt 8ma pc8 8 ? pe1 i/o 5vt 8ma pe1 83 pe ? i/o 5vt 8ma pe ? 8 ? pe3 i/o 5vt 8ma pe3 85 55 vdd33_ ? p 3.3 v vo ? tage for digita ? i/o 86 56 vss33_ ? p gro ? nd reference for digita ? i/o 87 pe ? i/o 5vt 8ma pe ? 88 pe5 i/o 5vt 8ma pe5 89 pe6 i/o 5vt 8ma pe6 90 pe7 i/o 5vt 8ma pe7 91 57 ? 1 pb6 ai/o 33v ? /8ma pb6 9 ? 58 ?? pb7 ai/o 33v ? /8ma pb7 93 59 ? 3 pb8 ai/o 33v ? /8ma pb8 9 ? 60 ?? pb9 ai/o 33v ? /8ma pb9 95 61 ? 5 pb10 ai/o 33v ? /8ma pb10 96 6 ? ? 6 pb11 ai/o 33v ? /8ma pb11 97 63 ? 7 vdda p 3.3 v ana ? og vo ? tage for adc and opa/ comparator 98 vref+ p adc positive reference vo ? tage has to be ? ower or eq ? a ? to vdda 99 vref- p adc negative reference vo ? tage has to be direct ?? connected to vssa 100 6 ? ? 8 vssa p gro ? nd reference for the adc and opa/ comparator note: 1. i = inp ? t ? o = o ? tp ? t ? a = ana ? og port ? p = power s ? pp ??? pu = p ??? - ? p ? bk = back- ? p domain ? . 5vt = 5 v to ? erant; 33v = 3.3 v to ? erant. 3. the gpios are in an af0 state after a v dd18 power on reset (por) except for the rtcout pin in the back ? p domain i/o. the rtcout pin is reset b ? the back ? p domain power-on-reset (porb) or b ? the back ? p domain software reset (bak_rst bit in bak_cr register). ? . the back ? p domain of the i/o pins have a so ? rce c ? rrent capabi ? it ? ? imitation of < 1ma @ v bat = 3.3v. rev. 1.00 30 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 electrical characteristics 4 electrical characteristics absolute maximum ratings the following table shows the absolute maximum ratings of the device. these are stress ratings only. s tresses beyond absolute maximum ratings may cause permanent damage to the device. note that the device is not guaranteed to operate properly at the maximum ratings. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. table 4. absolute maximum ratings symbol parameter min max unit v dd33 externa ? main s ? pp ?? vo ? tage v ss - 0.3 v ss + 3.6 v v dda externa ? ana ? og s ? pp ?? vo ? tage v ssa - 0.3 v ssa + 3.6 v v bat externa ? batter ? s ? pp ?? vo ? tage v ss - 0.3 v ss + 3.6 v v ldoin externa ? ldo s ? pp ?? vo ? tage v ss - 0.3 v ss + 3.6 v v in inp ? t vo ? tage on 5 v-to ? erant i/o v ss - 0.3 v ss + 5.5 v inp ? t vo ? tage on other i/o v ss - 0.3 v dd33 + 0.3 v t a ambient operating temperat ? re range - ? 0 +85 c t stg storage temperat ? re range -55 +150 c t ? maxim ? m j ? nction temperat ? re 1 ? 5 c p d tota ? power dissipation 500 mw v esd e ? ectrostatic discharge vo ? tage - h ? man bod ? mode - ? 000 + ? 000 v recommended dc operating conditions table 5. recommended dc operating conditions t a = ? 5 c, unless otherwise specifed. symbol parameter conditions min typ max unit v dd33 i/o operating vo ? tage ? .7 3.3 3.6 v v dda ana ? og operating vo ? tage ? .7 3.3 3.6 v v bat batter ? s ? pp ?? operating vo ? tage ? .7 3.3 3.6 v v ldoin ldo operating vo ? tage ? .7 3.3 3.6 v on-chip ldo voltage regulator characteristics table 6. ldo characteristics t a = ? 5 c, unless otherwise specifed. symbol parameter conditions min typ max unit v ldoout interna ? reg ?? ator o ? tp ? t vo ? tage v ldoin = 3.3v reg ?? ator inp ? t 1.71 1.8 1.89 v i ldoout o ? tp ? t c ? rrent v ldoin = ? .7v reg ?? ator inp ? t ? 00 ma c ldo external flter capacitor value for interna ? core power s ? pp ?? the capacitor va ?? e is dependent on the core power c ? rrent cons ? mption ? . ? 10 f rev. 1.00 31 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 electrical characteristics electrical characteristics power consumption table 7. power consumption characteristics t a = ? 5 c, unless otherwise specifed. symbol parameter conditions min typ max unit i dd s ? pp ?? c ? rrent (r ? n mode) v dd33 = v bat = 3.3 v ? hse = 8mhz ? pll = 1 ?? mhz ? f hclk = 7 ? mhz ? f pclk = 7 ? mhz ? a ?? periphera ? s enab ? ed 6 ? 7 ? ma v dd33 = v bat = 3.3 v ? hse = 8mhz ? pll = 1 ?? mhz ? f hclk = 7 ? mhz ? f pclk = 7 ? mhz ? a ?? periphera ? s disab ? ed ? 9 3 ? ma s ? pp ?? c ? rrent (s ? eep mode) v dd33 = v bat = 3.3 v ? hse = 8mhz ? pll = 1 ?? mhz ? f hclk = 0mhz ? f pclk = 7 ? mhz ? a ?? periphera ? s enab ? ed ? 3 50 ma v dd33 = v bat = 3.3 v ? hse = 8mhz ? pll = 1 ?? mhz ? f hclk = 0mhz ? f pclk = 7 ? mhz ? a ?? periphera ? s disab ? ed 8.5 1 ? ma s ? pp ?? c ? rrent (deep-s ? eep1 mode) v dd33 = v bat = 3.3 v ? a ?? c ? ock off (hse/pll/f hclk ) ? ldo in ? ow power mode ? lsi on ? rtc on 63 90 a s ? pp ?? c ? rrent (deep-s ? eep ? mode) v dd33 = v bat = 3.3 v ? a ?? c ? ock off (hse/pll/f hclk ) ? ldo off (dmos on) ? lsi on ? rtc on ? 0 ? 5 a s ? pp ?? c ? rrent (power-down mode) v dd33 = v bat = 3.3 v ? ldo off ? lse on ? lsi off ? rtc on a v dd33 = v bat = 3.3 v ? ldo off ? lse on ? lsi off ? rtc off a v dd33 = v bat = 3.3 v ? ldo off ? lse off ? lsi on ? rtc on a v dd33 = v bat = 3.3 v ? ldo off ? lse off ? lsi on ? rtc off 5 6 a i bat batter ? s ? pp ?? c ? rrent (power- down mode) v dd33 not present ? v bat = 3.3 v ? ldo off ? lse off ? lsi on ? rtc on ? a v dd33 not present ? v bat = 3.3 v ? ldo off ? lse off ? lsi on ? rtc off 3.9 a note: 1. hse means high speed externa ? osci ?? ator. hsi means 8mhz high speed interna ? osci ?? ator. ? . lse means ? ow speed externa ? osci ?? ator. lsi means 3 ? .768khz ? ow speed interna ? osci ?? ator. 3. rtc means rea ? time c ? ock. ? . code = whi ? e (1) { ? 08 nop } exec ? ted in f ? ash. rev. 1.00 3 ? of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 electrical characteristics reset and supply monitor characteristics table 8. lvd/bod characteristics t a = ? 5 c, unless otherwise specifed. symbol parameter conditions min typ max unit v bod brown o ? t detector vo ? tage ? .6 v v lvd vo ? tage of low vo ? tage detector lvds (note1) = 000 ? .7 v lvds (note1) = 001 ? .8 v lvds (note1) = 010 ? .9 v lvds (note1) = 011 3.0 v lvds (note1) = 100 3.1 v lvds (note1) = 101 3. ? v lvds (note1) = 110 3. ? v lvds (note1) = 111 3.5 v v por power on reset vo ? tage 1.36 v note: lvds feld is in pwrcu lvdcsr register external clock characteristics table 9. high speed external clock (hse) characteristics t a = ? 5 c, unless otherwise specifed. symbol parameter conditions min typ max unit f hse high speed externa ? osci ?? ator freq ? enc ? (hse) v dd33 = 3.3 v ? 16 mhz c hse recommended ? oad capacitance on xtalin and xtalout pins tbd pf r fhse recommended externa ? feedback resistor between xtalin and xtalout pins 1.0 m d hse hse osci ?? ator d ? t ? c ? c ? e ? 0 60 % i ddhse hse osci ?? ator c ? rrent cons ? mption v dd33 = 3.3 v ? t a = ? 5 c 0.96 ma i stbhse hse osci ?? ator s tandb ? c ? rrent v dd33 = 3.3 v ? t a = ? 5 c 0.1 a t suhse hse osci ?? ator s tart ? p time v dd33 = 3.3 v ? t a = ? 5 c ? ms rev. 1.00 33 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 electrical characteristics electrical characteristics table 10. low speed external clock (lse) characteristics t a = ? 5 c, unless otherwise specifed . symbol parameter conditions min typ max unit f lse low speed externa ? osci ?? ator fre - q ? enc ? (lse) v dd33 = v bat = 3.3 v 3 ? .768 khz c lse recommended ? oad capacitance on xtal3 ? kin and xtal3 ? kout pins tbd pf r flse recommended externa ? feedback resistor between xtal3 ? kin and xtal3 ? kout pins 10 m d lse lse osci ?? ator d ? t ? c ? c ? e ? 0 60 % i ddlse lse osci ?? ator operating c ? rrent v dd33 = v bat = 3.3 v ? lsesm = 0 (norma ? start ? p mode) 1.7 a i stblse lse osci ?? ator standb ? c ? rrent v dd33 = v bat = 3.3 v ? lsesm = 1 (fast start ? p mode) 3 8 a t sulse lse osci ?? ator start ? p time v dd33 = v bat = 3.3 v ? lsesm = 1 (fast start ? p mode) ? 00 ms note: the fo ?? owing pcb ? a ? o ? t g ? ide ? ines are recommended to increase the stabi ? it ? of the cr ? sta ? circ ? it for the hse/lse c ? ock: 1. the cr ? sta ? osci ?? ator sho ?? d be ? ocated as c ? ose as possib ? e to the mcu to minimise trace ? ength th ? s red ? cing parasitic capacitance. ? . use a gro ? nd p ? ane as a shie ? d ? nder the cr ? sta ? circ ? it to red ? ce the effects of noise interference. 3. ro ? te high freq ? enc ? signa ? s awa ? from cr ? sta ? osci ?? ator area to prevent crossta ? k. internal clock characteristics table 11. high speed internal clock (hsi) characteristics t a = ? 5 c, unless otherwise specifed. symbol parameter conditions min typ max unit f hsi high speed interna ? osci ?? ator freq ? enc ? (hsi) v dd33 = 3.3 v ? t a = - ? 0 c ~ +85c 8 mhz acc hsi hsi osci ?? ator freq ? enc ? acc ? rac ? factor ? -trimmed ? v dd33 = 3.3 v ? t a = - ? 0 c ~+85c -5 +5 % d hsi hsi osci ?? ator d ? t ? c ? c ? e v dd33 = 3.3 v ? f hsi = 8 mhz 35 65 % i ddhsi hsi osci ?? ator c ? rrent v dd33 = 3.3 v ? f hsi = 8 mhz 0.9 ? ma t suhsi hsi osci ?? ator start ? p time v dd33 = 3.3 v ? f hsi = 8 mhz ? hsircbl = 0 (hsi read ? co ? nter bits length 7 bits ) 17 s note: hsircbl feld is in pwrcu hsircr register table 12. low speed internal clock (lsi) characteristics t a = ? 5 c, unless otherwise specifed. symbol parameter conditions min typ max unit f lsi low speed interna ? osci ?? ator freq ? enc ? (lsi) v dd33 = v bat = 3.3 v ? t a = - ? 0 c ~ +85c ? 5 3 ? ? 3 khz i ddlsi lsi osci ?? ator operating c ? rrent v dd33 = v bat = 3.3 v ? t a = ? 5 c 1.0 ? a t sulsi lsi osci ?? ator s tart ? p time v dd33 = v bat = 3.3 v ? t a = ? 5 c 35 ms rev. 1.00 3 ? of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 electrical characteristics pll characteristics table 13. pll characteristics t a = ? 5 c, unless otherwise specifed. symbol parameter conditions min typ max unit f pllin pll inp ? t c ? ock ? 16 mhz f ck_pll pll o ? tp ? t c ? ock 8 1 ?? mhz t lock pll ? ock time tbd ms memory characteristics table 14. flash memory characteristics t a = ? 5 c, unless otherwise specifed. symbol parameter conditions min typ max unit n endu n ? mber of g ? aranteed program/erase c ? c ? es before fai ?? re. (end ? rance) t a = - ? 0 c ~ +85c ? 0 k c ? c ? es t ret data retention time t a = ? 5 c 100 years t prog word programming time t a = - ? 0 c ~ +85c ? 0 ? 0 s t erase page erase time t a = - ? 0 c ~ +85c ? 0 ? 0 ms t merase mass erase time t a = - ? 0 c ~ +85c ? 0 ? 0 ms i/o port characteristics table 15. i/o port characteristics t a = ? 5 c, unless otherwise specifed. symbol parameter conditions min typ max unit i il low ? eve ? inp ? t c ? rrent 3.3 v io v i = 0 v ? on-chip p ??? - ? p resister disab ? ed. 3 a 5 v-to ? erant io 3 a reset pin 3 a i ih high ? eve ? inp ? t c ? rrent 3.3 v io v i = v dd33 ? on-chip p ??? - down resister disab ? ed. 3 a 5 v-to ? erant io 3 a reset pin 3 a v il low ? eve ? inp ? t vo ? tage 3.3 v io -0.3 0.8 v 5 v-to ? erant io -0.3 0.8 v reset pin -0.3 0.8 v v ih high ? eve ? inp ? t vo ? tage 3.3 v io ? 3.6 v 5 v-to ? erant io ? 5.5 v reset pin ? 5.5 v v hys schmitt trigger inp ? t vo ? tage h ? steresis 3.3 v io ? 00 mv 5 v-to ? erant io ? 00 mv reset pin ? 00 mv rev. 1.00 35 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 electrical characteristics electrical characteristics symbol parameter conditions min typ max unit i ol low ? eve ? o ? tp ? t c ? rrent (gpio sink c ? rrent) 3.3 v io ? ma drive ? v ol = 0. ? v ? ma 3.3 v io 8 ma drive ? v ol = 0. ? v 8 ma 5 v-to ? erant io 8 ma drive ? v ol = 0. ? v 8 ma 5 v-to ? erant io 1 ? ma drive ? v ol = 0. ? v 1 ? ma back ? p domain io drive @ v bat = 3.3 v ? v ol = 0. ? v ? pc13 ? pc1 ?? pc15 ? ma i oh high ? eve ? o ? tp ? t c ? rrent (gpio so ? rce c ? rrent) 3.3 v i/o ? ma drive ? v oh = v dd33 - 0. ? v ? ma 3.3 v i/o 8 ma drive ? v oh = v dd33 - 0. ? v 8 ma 5 v-to ? erant i/o 8 ma drive ? v oh = v dd33 - 0. ? v 8 ma 5 v-to ? erant i/o 1 ? ma drive ? v oh = v dd33 - 0. ? v 1 ? ma back ? p domain io drive @ v bat = 3.3 v ? v ol = v dd33 - 0. ? v ? pc13 ? pc1 ?? pc15 1 ma v ol low ? eve ? o ? tp ? t vo ? tage 3.3 v ? ma drive io ? i ol = ? ma 0. ? v 3.3 v 8 ma drive io ? i ol = 8 ma 0. ? v 5 v-to ? erant 8 ma drive io ? i ol = 8 ma 0. ? v 5 v-to ? erant 1 ? ma drive io ? i ol = 1 ? ma 0. ? v v oh high ? eve ? o ? tp ? t vo ? tage 3.3 v ? ma drive io ? i oh = ? ma v dd33 - 0. ? v v 3.3 v 8 ma drive io ? i oh = 8 ma v dd33 - 0. ? v v 5 v-to ? erant 8 ma drive io ? i oh = 8 ma v dd33 - 0. ? v v 5 v-to ? erant 1 ? ma drive io ? i oh = 1 ? ma v dd33 - 0. ? v v r pu interna ? p ??? - ? p resistor 3.3 v i/o 3 ? 7 ? k 5 v-to ? erant i/o 38 89 k r pd interna ? p ??? -down resistor 3.3 v i/o ? 9 86 k 5 v-to ? erant i/o 35 107 k rev. 1.00 36 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 electrical characteristics adc characteristics table 16. adc characteristics t a = ? 5 c, unless otherwise specifed. symbol parameter conditions min typ max unit v dda operating vo ? tage ? .7 3.3 3.6 v v adcin a/d converter inp ? t vo ? tage range 0 v ref+ v v ref+ a/d converter reference vo ? tage v dda v dda v i adc c ? rrent cons ? mption v dda = 3.3 v 1 tbd ma i adc_dn power down c ? rrent cons ? mption v dda = 3.3 v 1 10 a f adc a/d converter c ? ock 0.7 1 ? mhz f s samp ? ing rate 0.05 1 mhz f adcconv a/d converter conversion time 1 ? 1/f adc c ? c ? es r i inp ? t samp ? ing switch resistance 1 k c i inp ? t samp ? ing capacitance no pin/pad capacitance inc ?? ded 5 pf t su start ? p ? p time 1 s n reso ?? tion 1 ? bits inl integra ? non- ? inearit ? error f s = 1 mhz ? v dda = 3.3 v ? 5 lsb dnl differentia ? non- ? inearit ? error f s = 1 mhz ? v dda = 3.3 v 1 lsb e o offset error 10 lsb e g gain error 10 lsb note: 1. g ? aranteed b ? design ? not tested in prod ? ction. 2. the fgure below shows the equivalent circuit of the a/d converter sample-and-hold input stage where c i is the storage capacitor ? r i is the resistance of the samp ? ing switch and r s is the o ? tp ? t impedance of the signa ? so ? rce v s . norma ??? the samp ? ing phase d ? ration is approximate ??? 1.5/f adc . the capacitance ? c i ? m ? st be charged within this time frame and it m ? st be ens ? red that the vo ? tage at its termina ? s becomes suffciently c ? ose to v s for acc ? rac ? . to g ? arantee this ? r s ma ? not have an arbitrari ?? ? arge va ?? e. rev. 1.00 37 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 electrical characteristics electrical characteristics sar adc c i sample r i r s v s figure 7. adc sampling network model the worst case occurs when the extremities of the input range (0v and vref) are sampled consecutively. in this situation a sampling error below ? lsb is ensured by using the following equation: i n iadc s r cf r ? < + )2ln( 5.1 2 where f adc is the adc clock frequency and n is the adc resolution (n = 12 in this case). a safe margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for in this simple model. if, in a system where the a / d co nverter is used, there are no rail-to-rail input voltage variations between consecutive sampling phases, rs may be larger than the value indicated by the equation above. rev. 1.00 38 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 electrical characteristics operational amplifer/comparator characteristics table 17. opa/cmp characteristics t a = ? 5 c, unless otherwise specifed. symbol parameter conditions min typ max unit v dda operating vo ? tage ? .7 3.3 3.6 v i opa/cmp t ? pica ? operating c ? rrent ? 30 a i opa/cmp_dn power down s ? pp ?? c ? rrent assign registers opaen = 0 and en_opaop = 0 0.1 a v ios inp ? t offset vo ? tage v dda = 3.3 v ? anof[5:0] = 100000 -15 15 mv v dda = 3.3 v ? after ca ? ibration -1 1 mv v ios_drift inp ? t offset vo ? tage drift t a = - ? 0 c ~ +85c 0.0 ? mv/c r input inp ? t resistance 10 m? gv vo ? tage gain 60 100 db u t unit-gain bandwidth r l =100k 1 ? 3 mhz r l =100k, c l =100pf 1. ?? v cm opa common mode vo ? tage range v dda = 3.3 v v ssa v dda C 1. ? v v ov opa o ? tp ? t vo ? tage swing v dda = 3.3 v v ssa + 0.3 v dda C 0.5 v sr s ? ew rate v dda = 3.3 v; o ? tp ? t capacitor ? oad c l =100pf 1.6 v/s t rt comparator response time v dda = 3.3 v; inp ? t overdrive = 10mv 1 s note: g ? aranteed b ? design ? not tested in prod ? ction. gptm/mctm characteristics table 18. gptm/mctm characteristics symbol parameter conditions min typ max unit f tm timer c ? ock so ? rce for gptm and mctm 7 ? mhz t res timer reso ?? tion time 1 f tm f ext externa ? sing ? e freq ? enc ? on channe ? 1 ~ ? 1/ ? f tm res timer reso ?? tion 16 bits rev. 1.00 39 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 electrical characteristics electrical characteristics i 2 c characteristics table 19. i 2 c characteristics symbol parameter standard mode fast mode fast mode plus unit min max min max min max f scl scl c ? ock freq ? enc ? 100 ? 00 1000 khz t scl(h) scl c ? ock high time ? .5 1.1 ? 5 0. ? 5 s t scl(l) scl c ? ock ? ow time ? .5 1.1 ? 5 0. ? 5 s t fall scl and sda fa ?? time 1.3 0.3 ? 0.135 s t rise scl and sda rise time 1.3 0.3 ? 0.135 s t su(sda) sda data set ? p time 500 1 ? 5 50 ns t h(sda) sda data ho ? d time 0 0 0 ns t su(sta) start condition set ? p time 500 1 ? 5 50 ns t h(sta) start condition ho ? d time 0 0 0 ns t su(sto) stop condition set ? p time 500 1 ? 5 50 ns note: 1. g ? aranteed b ? design ? not tested in prod ? ction. ? . to achieve 100khz standard mode ? the periphera ? c ? ock freq ? enc ? m ? st be higher than ? mhz. 3. to achieve ? 00khz fast mode ? the periphera ? c ? ock freq ? enc ? m ? st be higher than 8mhz. ? . to achieve 1mhz fast mode p ?? s ? the periphera ? c ? ock freq ? enc ? m ? st be higher than ? 0mhz. 5. the above characteristic parameters of the i ? c b ? s timing are based on: seq_filter = 01 and comb_ filter_en is disab ? ed. t su(sta) t h(sta) t fall t scl(l) t rise t scl(h) t h(sda) t su(sda) t su(sto) scl sda figure 8. i 2 c timing diagrams rev. 1.00 ? 0 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 electrical characteristics spi characteristics table 20. spi characteristics symbol parameter conditions min typ max unit f sck sck c ? ock freq ? enc ? f pclk / ? mhz t sck(h) sck c ? ock high time f pclk /8 ns t sck(l) sck c ? ock ? ow time f pclk /8 ns spi master mode t v(mo) data o ? tp ? t va ? id time 5 ns t h(mo) data o ? tp ? t ho ? d time ? ns t su(mi) data inp ? t set ? p time 5 ns t h(mi) data inp ? t ho ? d time 5 ns spi slave mode t su(sel) sel enab ? e set ? p time ? t pclk ns t h(sel) sel enab ? e ho ? d time ? t pclk ns t a(so) data o ? tp ? t access time 3 t pclk ns t dis(so) data o ? tp ? t disab ? e time 10 ns t v(so) data o ? tp ? t va ? id time ? 5 ns t h(so) data o ? tp ? t ho ? d time 15 ns t su(si) data inp ? t set ? p time 5 ns t h(si) data inp ? t ho ? d time ? ns sck (cpol = 0) sck (cpol = 1) mosi miso mosi miso t sck(h) t sck(l) t sck data valid data valid data valid data valid data valid data valid data valid data valid t v(mo) cpha = 0 cpha = 1 t h(mo) t h(mi) t su(mi) t v(mo) t h(mo) t su(mi) t h(mi) data valid data valid data valid data valid figure 9. spi timing diagrams - spi master mode rev. 1.00 ? 1 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 electrical characteristics electrical characteristics sck (cpol=0) sck (cpol=1) mosi miso t sck(h) t sck(l) t sck msb/lsb out msb/lsb in t v(so) t h(so) t su(si) t h(si) sel lsb/msb out lsb/msb in t a(so) t su(sel) t dis(so) t h(sel) figure 10. spi timing diagrams - spi slave mode with cpha=1 i 2 s characteristics table 21. i 2 s characteristics symbol parameter conditions min typ max unit i 2 s master mode t wsd(mo) ws o ? tp ? t to bclk de ? a ? tbd ns t dod(mo) data o ? tp ? t to bclk de ? a ? tbd ns t dis(mi) data inp ? t set ? p time tbd ns t dih(mi) data inp ? t ho ? d time tbd ns i 2 s slave mode t bch(si) bclk high p ?? se width tbd ns t bcl(si) bclk ? ow p ?? se width tbd ns t wss(si) ws inp ? t set ? p time tbd ns t dod(so) data o ? tp ? t to bclk de ? a ? tbd ns t dis(si) data inp ? t set ? p time tbd ns t dih(si) data inp ? t ho ? d time tbd ns rev. 1.00 ?? of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 electrical characteristics bclk ws sdo sdi t dis(mi) t dih(mi) t dod(mo) t wsd(mo) figure 11. timing of i 2 s master mode bclk ws sdo sdi t dis(si) t dih(si) t dod(so) t wss(si) t bch(si) t bcl(si) figure 12. timing of i 2 s slave mode rev. 1.00 ? 3 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 electrical characteristics electrical characteristics usb characteristics the usb interface is usb-if certifed C full speed. table 22. usb dc electrical characteristics symbol parameter conditions min typ max unit v dd33 usb operating vo ? tage 3.0 3.6 v v di differentia ? inp ? t sensitivit ? |usbdp-usbdm| 0. ? v v cm common mode vo ? tage range 0.8 ? .5 v v se sing ? e-ended receiver thresho ? d 0.8 ? .0 v v ol pad o ? tp ? t ? ow vo ? tage r l of 1.5k to v dd33 0 0.3 v v oh pad o ? tp ? t high vo ? tage ? .8 3.6 v v crs differentia ? o ? tp ? t signa ? cross-point vo ? tage 1.3 ? .0 v z drv driver o ? tp ? t resistance 10 c in transceiver pad capacitance ? 0 pf note: 1. g ? aranteed b ? design ? not tested in prod ? ction. 2. to be compliant with the usb 2.0 full-speed electrical specifcation, the usbdp pin should be pulled up with a 1.5k external resistor to a 3.0-to-3.6 v voltage s ? pp ?? . 3. the usb f ? nctiona ? it ? is ens ? red down to ? .7 v b ? t not the f ??? usb e ? ectrica ? characteristics which wi ?? experience degradation in the ? .7-to-3.0 v v dd33 vo ? tage range. ? . rl is the ? oad connected to the usb driver usbdp. t r t f 90% 90% 10% 10% fall time rise time v crs figure 13. usb signal rise time and fall time and cross-point voltage (v crs hqlwlrq table 23 usb ac electrical characteristics symbol parameter conditions min typ max unit t r rise time c l = 50 pf ? ? 0 ns t f fa ?? time c l = 50 pf ? ? 0 ns t r/f rise time / fa ?? time matching t r/f = t r / t f 90 110 % rev. 1.00 ?? of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 package information 5 package information note that the package information prov ided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to p ackaging is listed below. click o n the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product tape and reel specifcations) ? packing meterials information ? carton information rev. 1.00 ? 5 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 package information package information 48-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.35 ? bsc b 0. ? 76 bsc c 0.35 ? bsc d 0. ? 76 bsc e 0.0 ? 0 bsc f 0.007 0.009 0.011 g 0.053 0.055 0.057 h 0.063 i 0.00 ? 0.006 ? 0.018 0.0 ?? 0.030 k 0.00 ? 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 9.0 bsc b 7.0 bsc c 9.0 bsc d 7.0 bsc e 0.5 bsc f 0.17 0. ?? 0. ? 7 g 1.35 1. ? 0 1. ? 5 h 1.60 i 0.05 0.15 ? 0. ? 5 0.60 0.75 k 0.09 0. ? 0 0 D 7 rev. 1.00 ? 6 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 package information 64-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.35 ? bsc b 0. ? 76 bsc c 0.35 ? bsc d 0. ? 76 bsc e 0.016 bsc f 0.005 0.007 0.009 g 0.053 0.055 0.057 h 0.063 i 0.00 ? 0.006 ? 0.018 0.0 ?? 0.030 k 0.00 ? 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 9.00 bsc b 7.00 bsc c 9.00 bsc d 7.00 bsc e 0. ? 0 bsc f 0.13 0.18 0. ? 3 g 1.35 1. ? 0 1. ? 5 h 1.60 i 0.05 0.15 ? 0. ? 5 0.60 0.75 k 0.09 0. ? 0 0 D 7 rev. 1.00 ? 7 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 package information package information 100-pin lqfp (14mm14mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.630 bsc b 0.551 bsc c 0.630 bsc d 0.551 bsc e 0.0 ? 0 bsc f 0.007 0.009 0.011 g 0.053 0.055 0.057 h 0.063 i 0.00 ? 0.006 ? 0.018 0.0 ?? 0.030 k 0.00 ? 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 16.00 bsc b 1 ? .00 bsc c 16.00 bsc d 1 ? .00 bsc e 0.50 bsc f 0.17 0. ?? 0. ? 7 g 1.35 1. ? 0 1. ? 5 h D D 1.60 i 0.05 0.15 ? 0. ? 5 0.60 0.75 k 0.09 0. ? 0 0 D 7 rev. 1.00 ? 8 of ? 8 ???? ??? ? 01 ? 3 ? -bit arm ? cortex?-m3 mcu ht3 ? f1656/ht3 ? f1655 cop ? right ? ? 01 ? b ? holtek semiconductor inc. the information appearing in this data sheet is be ? ieved to be acc ? rate at the time of p ? b ? ication. however ? ho ? tek ass ? mes no responsibi ? it ? arising from the ? se of the specifcations described. the applications mentioned herein are used solely for the p ? rpose of i ??? stration and ho ? tek makes no warrant ? or representation that s ? ch app ? ications wi ?? be s ? itab ? e witho ? t f ? rther modification ? nor recommends the ? se of its prod ? cts for app ? ication that ma ? present a risk to h ? man ? ife d ? e to ma ? f ? nction or otherwise. ho ? tek's prod ? cts are not a ? thorized for ? se as critica ? components in ? ife s ? pport devices or s ? stems. ho ? tek reserves the right to a ? ter its products without prior notifcation. for the most up-to-date information, please visit o ? r web site at http://www.ho ? tek.com.tw. |
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